High quantum efficiency and broad spectral range are desirable features for solid state image sensors. A preferred method to increase quantum efficiency is to decrease the absorption of light by material or regions of the device which do not produce signal charge. Backside illumination of sensors can accomplish this purpose provided the device wafer is thinned and provided the electrical potential of the back surface is controlled. Various procedures have been reported for backside thinning and for control of the back surface potential. See J. Janesick et al. "CCD Pinning Technologies", SPIE Optical Sensors and Electronic Photography, Vol. 1071-15, Los Angeles, Jan 16-18, (1989); C. M. Huang et al., "A Wafer-Scale Thinning Process for High-Performance Silicon Devices", Abstract No. 481, 174th Electrochemical Society Mtg., 88-2, 705 (1988); T. W. Edwards and R. S. Pennypacker, U.S. Pat. No. 4,266,334, May 21, 1981; and M. Blouke et al., "Large format, high resolution image sensors", Optical Engineering, Vol. 26, No. 9, 837, (1987). However, these methods are complex and generally involve substantial processing after imager fabrication. Existing fabrication methods thin the device wafer after the devices have received most of the steps involved in their manufacture. Yield losses incurred due to thinning and backside accumulation operations are expensive since a great deal of processing has been invested in the devices prior to thinning. In addition, some methods require contacting of the device bond pads from the wafer backside. This involves aligning backside masks to the frontside device structures and etching contact holes to the bond pads. This is a complex and expensive process. Yield loss is also substantial. Also, some processing techniques degrade device performance and/or do not produce reliable results.